1. Technical Field
The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods and arrangements for etching a polysilicon gate layer in a memory device.
2. Background Art
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. As the devices and features shrink, new problems are discovered that require new methods of fabrication and/or new arrangements.
A flash or block erase Electrically Erasable Programmable Read Only Memory (flash EEPROM) semiconductor memory includes an array of memory cells that can be independently programmed and read. The size of each memory cell, and therefore the memory array, is made small by omitting select transistors that would enable the cells to be erased independently. The array of memory cells is typically aligned along a bit line and a word line and erased together as a block. An example of a memory of this type includes individual metal oxide semiconductor (MOS) memory cells, each of which includes a source, drain, floating gate, and control gate to which various voltages are applied to program the cell with a binary 1 or 0. Each memory cell can be read by addressing it via the appropriate word and bit lines.
An exemplary memory cell 8 is depicted in FIG. 1A. As shown, memory cell 8 is viewed in a cross-section through the bit line. Memory cell 8 includes a doped substrate 12 having a top surface 11, and within which a source 13a and a drain 13b have been formed by selectively doping regions of substrate 12. A tunnel oxide 15 separates a floating gate 16 from substrate 12. An interpoly dielectric 24 separates floating gate 16 from a control gate 26. Floating gate 16 and control gate 26 are each electrically conductive and typically formed of polysilicon.
On top of control gate 26 is a silicide layer 28, which acts to increase the electrical conductivity of control gate 26. Silicide layer 28 is typically a tungsten silicide (e.g., WSi.sub.2), that is formed on top of control gate 26 prior to patterning, using conventional deposition and annealing processes.
As known to those skilled in the art, memory cell 8 can be programmed, for example, by applying an appropriate programming voltage to control gate 26. Similarly, memory cell 8 can be erased, for example, by applying an appropriate erasure voltage to source 13a. When programmed, floating gate 16 will have a charge corresponding to either a binary 1 or 0. By way of example, floating gate 16 can be programmed to a binary 1 by applying a programming voltage to control gate 26, which causes an electrical charge to build up on floating gate 16. If floating gate 16 does not contain a threshold level of electrical charge, then floating gate 16 represents a binary 0. During erasure, the charge is removed from floating gate 16 by way of the erasure voltage applied to source 13a.
FIG. 1B depicts a cross-section of several adjacent memory cells from the perspective of a cross-section through the word line (i.e., from perspective A, as referenced in FIG. 1A). In FIG. 1B, the cross-section reveals that individual memory cells are separated by isolating regions of silicon dioxide formed on substrate 12. For example, FIG. 1B shows a portion of a floating gate 16a associated with a first memory cell, a floating gate 16b associated with a second memory cell, and a floating gate 16c associated with a third memory cell. Floating gate 16a is physically separated and electrically isolated from floating gate 16b by a field oxide (FOX) 14a. Floating gate 16b is separated from floating gate 16c by a field oxide 14b. Floating gates 16a, 16b, and 16c are typically formed by selectively patterning a single conformal layer of polysilicon that was deposited over the exposed portions of substrate 12, tunnel oxide 15, and field oxides 14a-b. Interpoly dielectric later 24 has been conformally deposited over the exposed portions of floating gates 16a-c and field oxides 14a-b. Interpoly dielectric layer 24 isolates floating gates 16a-c from the next conformal layer which is typically a polysilicon layer that is patterned (e.g., along the bit line) to form control gate 26. Interpoly dielectric layer 24 typically includes a plurality of films, such as, for example, a bottom film of silicon dioxide, a middle film of silicon nitride, and a top film of silicon dioxide. This type of interpoly dielectric layer is commonly referred to as an oxide-nitride-oxide (ONO) layer.
The continued shrinking of the memory cells, and in particular the basic features depicted in the memory cells of FIGS. 1A-B, places a burden on the fabrication process to deposit and subsequently pattern a layer stack to form a floating gate/control gate structure, without creating deleterious effects within the resulting memory cells. Of particular concern, is the need to control the deposition and patterning process associated with the layer stack. In particular, there is a concern of providing accurate alignment to minimize the risk of introducing impurities into a substrate during channel implant.
FIGS. 2A and 2B are diagrams summarizing a conventional technique of forming the floating gate 16, viewed from a word line cross-section. As shown in FIG. 2A, the polysilicon layer 16 is etched to form the floating gates 16a, 16b, and 16c by depositing a layer of photoresist 40 overlying on the polysilicon layer 16 to a thickness of about 9700 Angstroms (.ANG.). The deposited photoresist layer 40 is then patterned using conventional deep ultraviolet (DUV) photolithography techniques to form spaces 42. The polysilicon layer 16 typically has a thickness of about 900 Angstroms. The patterned resist layer 40 having the spaces 42 is used as a mask for etching the polysilicon layer 16, resulting in the structure of FIG. 2B having the etched polysilicon layer 16a, 16b, and 16c. The spacing (S.sub.1) of the exposed region 50 of the field oxide 14a equals the limit of current DUV photolithography techniques, around 0.24 microns.
Following etching of the polysilicon layer 16, the resist mask pattern 44 loses about 100 to 200 Angstroms of resist during the polysilicon etch. The resist mask pattern 44' is then used as an implant mask during implantation of impurities 46 into the exposed regions 48 of the etched polysilicon layer 16a, 16b, and 16c.
As shown in FIG. 2B, some of the impurities 46 are implanted into the resist layer 44'. Hence, the resist layer 40 must have sufficient thickness (e.g., 9700 Angstroms) to protect the non-exposed portions of the semiconductor wafer. Hence, the resist mask pattern 44', when properly aligned with the center of the isolation region 14a and 14b, causes the impurities 46 to be implanted only into the exposed regions 48 of the polysilicon layer 16, and the exposed portion 50 of the isolation region 14.
A primary concern is that the resist mask pattern 44' is properly aligned with the isolation region 14 to prevent the impurities 46 from entering the active region 52 of the substrate 12, which is bounded by the isolation regions 14a and 14b. Since the implant of impurities 46 is a relatively high energy implant, it is desirable to use the combination of the polysilicon layer 16 and the resist layer 42 block the impurities from entering the active region 52. However, if misregistration occurs such that the mask pattern is not properly overlaid with the isolation region 14b, illustrated in FIG. 2B as the dotted pattern line 44", the impurities may enter the source/drain active region 52 due to misregistration (i.e., misalignment) of the resist mask pattern 44".
The use of the thick resist layer 40 having a thickness of about 9700 Angstroms causes alignment problems in that the process margin for properly overlaying the resist mask pattern 44 with the isolation region 14 is very small. Hence the masking process may need to be performed two to three times per lot in order to attain the appropriate overlay. The spacing (S.sub.1) is also limited to no less than 0.25 microns since the formation of small spaces using a thick resist layer 40 is relatively difficult.